Speaker: Dani Shaket
Affiliation: Dept. of Electrical Engineering Technion
Asymmetric chip-multiprocessors (ACMPs) can increase power-efficiency by executing diverse workloads on suitable cores. Matching workloads to cores with ever-changing workload behaviors is a challenge. Practical solutions so far assume ordering of core strength from simple “little” energy-efficient cores to complex “big” ones, which provide high performance for compute-heavy workloads. This approach allows relatively straightforward workload-to-core assignment.
In this work, we argue that restricting the cores design space to linear ordering limits the potential of ACMP. We examine the notion of using asymmetric specialized cores to achieve higher power-efficiency.
Managing the execution of a multi-core system with a high diversity of cores and workloads is a complex task. In order to perform this task efficiently, we propose a centralized history-based lookup mechanism that shares execution information among cores. During workload execution, each core produces micro-architecture-independent signatures and corresponding performance attributes. The signatures are generated using workload behavior, and not from the impact on the core. Workloads that share the same signature are expected to have similar performance characteristics when executed on the same core. We find a micro-architecture-independent signature structure that enables accurate
prediction based on behavioral resemblance.
Our proposed system which consists of six cores and a trained predictor, simulated using GEM5 and McPAT, shows up
to 40% power-performance gain with 13% on average for the tested SPEC2006 benchmarks in comparison to
big.LITTLE based ACMP.