The Design and Productization of Digital RF Transceiver ICs

The Design and Productization of Digital RF Transceiver ICs
March, 12, 2014
Room 1003 Electrical Eng. Building Technion City

2-Day Intensive Course , Wednesday – Thursday, March 12-13 , 2014
As increasing amounts of functionality are offered in wireless consumer-market devices at ever reducing costs, the wireless transceiver system-on-chip (SoC) solutions within them are becoming more digital and software based. This allows them to leverage the benefits of the nanometer CMOS fabrication processes used for the processors and memory in these devices, while avoiding the shortcomings found in traditional RF design.

This intense 2-day course presents the various aspects of this recent approach, including system-architecture, system and circuit level design methodologies, productization, and organizational aspects.   The architectures covered will include wideband/RF data converters, all-digital PLL, and polar and quadrature transmitters.

Built-in calibration/compensation/testing in transceiver SoCs are emphasized as a key element in achieving cost effectiveness and competitiveness.


Dr. Oren Eliezer  


Dr. Oren Eliezer has over 25 years of experience in the design and productization of communication systems and chips for telecom and wireless applications.

He received his BSEE and MSEE degrees from the Tel-Aviv University in 1988 and in 1997, focusing on communication systems and signal processing, and his PhD in microelectronics from the University of Texas at Dallas in 2008.

After serving for 6 years as an engineer in the IDF, he co-founded Butterfly Communications, which was acquired by Texas Instruments (TI) in 1999.

He was relocated by TI to Dallas in 2002, where he was elected senior member of the technical staff, and took part in the development of TI’s digital-radio-processor (DRP) technology and in digital-signal processing techniques for built-in compensation and testing in wireless SoCs.

He joined Xtendwave in Dallas in 2009, where he received several government research grants and was responsible for redesigning the US government’s atomic-clock broadcast (WWVB).

He has authored and coauthored over 50 journal and conference papers and over 45 patents, and has given over 40 invited tutorials related to communication system design and productization.

He is currently the chief technology officer at Xtendwave and participates in the research at the Texas Analog Center of Excellence (TxACE) at UTD.  He is a technical program committee member for the IEEE RFIC conference and has chaired several local IEEE conferences.



Day 1 –   Wednesday,  March 12th  2014

09:00 – 10:30         Fundamentals of Digital-Radio Architectures

10:30 – 10:45         Break

10:45 – 12:15         The All-Digital PLL (ADPLL) and its use in Digital Transceivers

12:15 – 13:30         Lunch

13:30 – 15:00         Examples for Digital Receivers and Transmitters (Polar and Cartesian)

15:00 – 15:15         Break

15:15 – 17:00         Example  –  Digital Receiver for Atomic Clock Broadcast (WWVB)


Day 2 –   Thursday,  March 13th  2014

09:00 – 10:30         Built-in Calibration and Compensation (“Self-Healing”)

10:30 – 10:45         Break

10:45 – 12:15         Fundamentals of Economical Manufacturability (BiSC and BiST)

12:15 – 13:30         Lunch

13:30 – 15:00         Designing for Self-Interference Mitigation

15:00 – 15:15         Break

15:15 – 17:00         Examples and Concluding Discussion


Prerequisites and Teaching Style:

Course attendees are assumed to be familiar with the basics of communication system design, and may be either students or engineers involved in system-level/algorithm and/or circuit-level design of RF transceivers.

The course will be given in Hebrew, and examples/problems will be used to verify the understanding and allow for interactive participation.


The course is free of charge to ACRC member Companies, Intel, Marvell and Mellanox and to EE Students (undergraduate and graduate)

Non-ACRC members will be charged 1000 Shekels+VAT.