Thermal and noise effects in nanometer CMOS-SOI devices and circuits

Thermal and noise effects in nanometer CMOS-SOI devices and circuits
March, 05, 2018
Room 1061 Electrical Eng. Building Technion City

Electro-optics and Microelectronics Seminar

Graduate Seminar

Speaker: Maria Malits
Affiliation: Electrical Eng., Technion

Nowadays, CMOS-SOI is emerging as a promising solution to continue the CMOS scaling allowing low-power, high temperature and “system on chip” applications as well as CMOS-SOI-MEMS/NEMS unique sensing systems for IR and THz imagers. The advantages of SOI technology over standard CMOS are: low power consumption, high operation frequency and high temperature of operation for a given technology node due to the very low source and drain junction capacitances, no body effect and soft-error immunity. While the advantage and importance of CMOS-SOI is wellestablished, there are two major limiting issues associated with this technology: thermal effects and low-frequency noise.
The role of temperature in Very/Ultra Large Scale Integration (VLSI/ULSI) chips is well-established by now. When the level of power consumption becomes relatively high, a designer has to consider, at the design stage, the effect of temperature on the circuit operation, especially when using CMOS-SOI technology. In CMOS-SOI technology the buried oxide layer introduces a thermal barrier that enhances self and coupled heating effects, degrading the circuit performance. For that reason, it’s important to consider the effect of temperature on the circuit operation at early design stages.
This research addresses the existing gap between the electronic VLSI/ULSI design and the physical aspect of temperature influencing the design. We identify this existing gap as one of the crucial aspects that hinder progress in the field of VLSI.
The main contribution of this study is a proposal for a novel method for on chip thermal management, where the thermal issues are addressed at the initial design phase This study aims to use the standard transistors in the technology under study (CMOS-SOI) as built-in temperature sensors. For that purpose, we developed unique and novel local chip temperature measurement method based on “Threshold Voltage Thermometry”. The method was implemented by using a CMOS-SOI Vt extractor circuit to extract transistor threshold voltage on-line.
This work provides a new Thermal Management approach, enabling designers to take into account the physical aspects of temperature in early design stage.

* PhD. Student under the supervision of Prof. Yael Nemirovsky