Loren Jammal


Viterbi Faculty of Electrical Engineering, Technion

Analyzing the interaction of I/O and performance in multiprocessors

In Big Data environment, off-chip bandwidth is a potential bottleneck in modern computer architectures. Multi-core machine, in which storage is shared among many cores, increases the bandwidth demand even further. Reaching the bandwidth limitation will decrease performance. The goal of this work is to comprehend the impact of the number of running processes on the performance of multiprocessors systems for applications which mix I/O and compute. The behaviors of such applications is investigated by addressing the interplay between the number of processes running in parallel, the maximum bandwidth limit of the storage and the buffer size of the I/O read system call. To this end, we developed an analytical model to estimate the system's execution time and the consumed storage bandwidth. Such a model will enable optimizing the number of running processes and the buffer size while keeping the architectural resources balanced.
Biography: * סטודנטית לתואר שני בהנחיית פרופסור אורי וייזר.

Date: Sun 01 Jul 2018

Start Time: 14:30

1061 | Electrical Eng. Building