Viterbi Faculty of Electrical Engineering, Technion
Characterizing a Data Routing Algorithm for Fault-Tolerant Real-Time NoC Systems
The Network-on-chip is the prominent interconnect method for many-processor architectures. The use of NoC for real-time fault-tolerant applications requires methods of guaranteeing both fault tolerance and deadline compliance. One of the tools to facilitate these requirements are adaptive routing algorithms that know how to circumvent faulty elements in the NOC. However, such algorithms to date are not acceptable for real-time purposes. This work introduces a routing algorithm for real-time fault tolerance, TOLEREAL, that outperforms current solutions in the task of real-time fault tolerant applications on NoC. Its superiority by simulation using a dedicated NoC simulator called HNOCS. This simulator was adapted and improved to enable various trace inputs, routing based on routing tables, and buffering and retransmission of messages using the minimum amount of storage possible. The results of the simulation show clearly that TOLEREAL has significantly lower end-to-end latencies than current solutions, which means meeting tighter deadlines, enabling compatibility of hardware for more hard real-time applications. The results are also compared to the ideal routing in every situation, including a faulty NOC, and are shown to be according to expectations and significantly tighter than previous work. Lior Barlev is a Master student of Prof. Avi Mendelson.
Date: Thu 28 Jun 2018
Start Time: 11:30
1061 | Electrical Eng. Building