Lecturer:

Nishil Talati

Affiliation:

Viterbi Faculty of Electrical Engineering, Technion

Design of a Memory Controller to Support Processing in Memory using Resistive RAM (RRAM)

Given technological constraints of memory, the memory controller in a computing system is responsible for intelligently scheduling memory accesses to optimize system performance and energy efficiency. Existing memory controllers target charge-based DRAM, which has been the technology choice for building main memory since several decades, however, scaling it to lower technology nodes is becoming increasingly costly because of several problems such as over-fetch, refresh, low energy efficiency, and on-chip error correction. Furthermore, since conventional DRAM memory cells cannot process data, modern computing systems suffer from high latency and energy of data transfer between CPU and memory, commonly known as the von Neumann bottleneck. In this research, I propose to use resistance-based emerging memory technology called Resistive RAM (RRAM) to build main memory because of its several advantages such as low cost, better scalability, and higher density. Despite these attractive features, some of the shortcomings of RRAM include high access latency and switching energy, and I propose to address them by designing a customized memory controller for RRAM. While most previous RRAM designs use a traditional DRAM-based memory controllers, which cannot unleash full potential for RRAM, I experimentally show using SPEC CPU2006 benchmarks that a memory controller for RRAM that is designed around specific technological constraints of RRAM can achieve DRAM-like memory performance and energy efficiency. In addition, RRAM also provides opportunity to perform data processing using the memory cells themselves because of their resistive nature. I further extend proposed memory controller to support processing-in-memory (PIM) instructions using a technique called MAGIC that enables computation without reading data out of the memory array. In this talk, I will show how such fast and energy efficient memory system coupled with PIM capabilities paves a way to alleviate the von Neumann bottleneck for data parallel workloads. Advisor: Asst. Prof. Shahar Kvatinsky.

Date: Wed 16 May 2018

Start Time: 14:30

1061 | Electrical Eng. Building