Graduate Seminar

Graduate Seminar
Speaker:

Oron Port

Affiliation:

Viterbi Faculty of Electrical Engineering, Technion

DFiant: A Dataflow Hardware Description Language

Since the dawn of digital hardware design, the most prominent hardware description model has been the register-transfer level (RTL) design abstraction. The main drawback of the RTL model is its coupling between functionality and timing constraints, resulting in a verbose and less portable code. Two main approaches were taken to mitigate these issues. One approach introduces high-level RTL languages (e.g., Chisel) to improve code expressiveness, but still binds the design to specific timing and device constraints. The other approach relies on high-level synthesis (HLS) tools (e.g., Vivado HLS) that employ software programming languages to abstract over registers. However, these languages loose fine grain hardware control and their inherent sequential semantics inhibit parallel hardware expressiveness. In our work we propose a new dataflow hardware description abstraction layer which covers the numerous synthesizable uses of RTL constructs and replaces them with higher-level abstractions. We also present DFiant, a Scala-embedded HDL that applies the dataflow semantics to decouple design functionality from its constraints. DFiant provides a strong bit-accurate type safe foundation to describe hardware in a very concise and portable fashion. The DFiant compiler can automatically pipeline designs to meet performance requirements and produce synthesizable RTL code. * PhD Seminar under the supervision of Prof. Yoav Etsion and Prof. Uri Weiser. Zoom link: https://technion.zoom.us/j/96294405624

Date: Tue 09 Feb 2021

Start Time: 14:00

End Time: 15:00

ZOOM Meeting | Electrical Eng. Building