Lecturer:

Per Stenström

Affiliation:

Chalmers University of Technology, Goteborg, Sweden

Microarchitecture Optimizations through Relaxation of Precision of Floats in GPUs

Reducing the precision of floating-point values can improve performance and/or reduce energy expenditure in GPUs. However, reducing the precision level of floating-point values in a controlled fashion needs support both at the compiler and at the microarchitecture level. At the compiler level, a method is needed to automate the reduction of precision of each floating-point value. At the microarchitecture level, a lower precision of each floating-point register can allow more floating-point values to be packed into a register file allowing more threads to be supported with the same register resources, hence improving performance. In this talk, I will present an automated precision-selection method and a novel GPU register file organization that can store floating-point register values at arbitrary precisions densely. The automated precision-selection method uses a data-driven approach for setting the precision level of floating-point values, given a quality threshold and a representative set of input data. By allowing a small, but acceptable, degradation in output quality, our method can remove a significant amount of the bits needed to represent floating-point values in the investigated kernels (between 28% and 60%). We show that the proposed register file improves performance by up to 40%, 12% on average, and performs as well as a twice as big register file while only using 30% more transistors than the original register file. Bio Per Stenstrom is professor at Chalmers University of Technology. His research interests are in parallel computer architecture. He has authored or co-authored four textbooks, more than 150 publications and ten patents in this area. He has been program chairman of several top-tier IEEE and ACM conferences including IEEE/ACM Symposium on Computer Architecture and acts as Senior Associate Editor of ACM TACO and Associate Editor-in-Chief of JPDC. He is a Fellow of the ACM and the IEEE and a member of Academia Europaea, the Royal Swedish Academy of Engineering Sciences and the Royal Spanish Academy of Engineering Science.

Date: Tue 13 Nov 2018

Start Time: 13:30

End Time: 14:30

1061 | Electrical Eng. Building

Inviter: פרופסור אורי וייזר