Viterbi Faculty of Electrical Engineering, Technion
MIXER FIRST RECEIVER FRONT END DESIGN AND IMPLEMENTATION FOR ULTRA LOW POWER RECEIVER SYSTEMS
The availability of unlicensed 7GHz band around 60GHz has motivated research and design of high data-rate communication systems up to several giga bits per- second in CMOS technologies. The critical blocks of the receiver front-end, are low noise amplifiers (LNA) and mixers. LNA in general can consume high DC power to achieve high gain and low Noise Figure (NF), and power consumption is of great importance in MIMO transceivers systems. Due to these issues with LNA, mixer first receivers have been developed, eliminating the need for LNA, with mixers that can achieve a good noise and gain performance and low power consumption without LNA. This work focuses on IQ mixer first receiver architecture at 60GHz, IQ receiver architecture is used to reject the image signal at the RF port. The receiver consists of symmetrical I and Q stages, an on-chip quadrature hybrid providing the 90º phase shift between the I and Q signals, and two differential mixer stages mixer biased at subthreshold for low DC power consumption due to the low DC power consumption at this region. The receiver architecture is targeted for low LO to RF leakage and low LO drive. The complete circuit achieves NF of 10.2dB, and conversion gain of 21dB with total power consumption of 2mW which is very low compared to other published designs. The small size and low power consumption of this design enables large array integration for the next generation of the communication system (5G) applications. The receiver test chip was fabricated in TSMC28nm process. * MSc seminar under supervision of Prof. Emanuel Cohen.
Date: Tue 03 Dec 2019
Start Time: 14:30
End Time: 15:30
1061 | Electrical Eng. Building